A method of delay fault test generation
25th ACM/IEEE, Design Automation Conference.Proceedings 1988.
It has been observed that random testing for delay faults can result in test sets of excessive length and high simulation costs. Consequently, we propose an efficient deterministic method of delay fault test generation. For most common circuits, our proposed technique has a time complexity which is polynomial in the size of the circuit, as opposed to existing deterministic methods which, for nearly all circuits, are exponential. We define a type of transition path, the fully transitional path,
... transitional path, F W , and demonstrate that it has several useful properties. An FTP can be created by applying a vector pair derived from a stuck-at test for a primary input, a technique introduced in [ 11. We extend this method by using an alternate representation for switching functions, the binary decision diagram, to generate graphs representing stuck-at tests. The concept of free variables is defined as a tool for deriving several FTPs from one stuck-at test. Preliminary results are presented which indicate that our method provides a higher robust delay fault coverage than psuedorandom patterns at less than one-fifth the cost. Also, since vector pairs cannot be applied to combinational circuits using standard scan design, a simple scannable latch is introduced to facilitate this task. 25th ACM/IEEE Design Automation Conference@ CH2540-3/88/oooO/oosO$01 .OO 0 1988 IEEE