A 300 GHz PLL in an InP HBT technology

Munkyo Seo, Miguel Urteaga, Mark Rodwell, Myung-Jun Choe
2011 2011 IEEE MTT-S International Microwave Symposium  
We present a 300 GHz fundamental PLL, based on a 300 GHz VCO, 2:1 dynamic frequency divider, fifth-order sub-harmonic phase detector, and active loop filter, fabricated in an InP HBT technology. The PLL achieves locking from 300.76 to 301.12 GHz, with -23 dBm of output power and -78 dBc/Hz of phase noise at a 100 KHz offset, while consuming 301.6 mW. The PLL occupies 0.84 mm 2 including pads. This work represents the highest frequency PLL reported thus far, 2× to 3× faster than previously reported PLLs.
doi:10.1109/mwsym.2011.5972924 fatcat:jlywgv2d6bhkbcr4ncag6vs6zm