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A Hardware Design Language for Timing-Sensitive Information-Flow Security
2015
SIGPLAN notices
Information security can be compromised by leakage via lowlevel hardware features. One recently prominent example is cache probing attacks, which rely on timing channels created by caches. We introduce a hardware design language, SecVerilog, which makes it possible to statically analyze information flow at the hardware level. With SecVerilog, systems can be built with verifiable control of timing channels and other information channels. SecVerilog is Verilog, extended with expressive type
doi:10.1145/2775054.2694372
fatcat:c2fvcf2jwzhzvg2hqqzfdlsmtm