Test-point insertion: scan paths through functional logic

Chih-Chang Lin, M. Marek-Sadowska, Kwang-Ting Cheng, M.T.-C. Lee
1998 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are added to the actual design. We propose a low-overhead scan design methodology that employs a new test-point insertion technique. Unlike the conventional test-point insertion, where test points are used directly to increase the controllability and observability of the selected signals, the test points are used here to
more » ... lish scan paths through the functional logic. The proposed technique reuses the functional logic for scan operations; as a result, the design-fortestability overhead on area or timing can be minimized. We show an algorithm that uses the new test-point insertion technique to reduce the area overhead for the full-scan design. We also discuss its application to the timing-driven partial-scan design.
doi:10.1109/43.720319 fatcat:cx72aafyg5bbdn75i5n3ks6x6m