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Test-point insertion: scan paths through functional logic
1998
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are added to the actual design. We propose a low-overhead scan design methodology that employs a new test-point insertion technique. Unlike the conventional test-point insertion, where test points are used directly to increase the controllability and observability of the selected signals, the test points are used here to
doi:10.1109/43.720319
fatcat:cx72aafyg5bbdn75i5n3ks6x6m