Introduction : In order to achieve dynamic random access memory (DRAM) with high density and high performance, abrupt scaling down of memory device is necessary. But lithography tool cannot follow up memory device scaling down. Double patterning technology (DPT) has been reported as a promising candidate to extend lithography limit [1, 2]. But DPT has a technical problem of pattern to pattern overlay [3]. To overcome overlay problems, cross double patterning technology (cross DPT) in which

more »

... d pattern is perpendicular to first one is introduced. In this paper, for the first time, memory cell capacitor using cross DPT is successfully developed. Process integration and electrical characteristics of memory cell capacitor using cross DPT is presented. Process Integration of Memory Cell Capacitor using Double Patterning Technology : DPT has been developed to overcome the limitation of lithography by patterning twice. Fig. 1 shows schematic diagram of DPT compared to single exposure technique (SET). DPT realizes patterning with half pitch size by patterning twice in pitch size. Second patterning mask is shifted by half pitch size. By doing this, the pitch can be reduced by a half as long as pattern to pattern overlay can be controlled well. Cross DPT in which second pattern is perpendicular to first one was introduced to overcome this problem of conventional DPT. Schematic diagram of cross DPT is shown in Fig. 2 . Second patterning mask is rotated by 90 degree therefore pattern to pattern overlay in cross DPT is not as critical as in conventional DPT. Fig. 3 shows process flows to make cell capacitor using DPT. After mold oxide is deposited for the formation of capacitor, photo lithography and etching process using DPT follow to make the hole of cell capacitor. After forming storage materials, cylinder type capacitor is formed by lift-off process to remove the mold oxide between capacitors. Dielectric films are deposited and finally TiN film is deposited as top electrode. Fig. 4 shows top view scanning electron microscope (SEM) images of process flow for cell capacitor using cross DPT. The capacitor using DPT has more rectangular shape than that of SET because contact hole of capacitor is formed by cross line patterns. Fig. 5 shows cross sectional transmission electron microscope (TEM) images of cell capacitor using DPT. Dielectric films are deposited uniformly in the top and bottom region of cylinder as shown in Fig. 5(b) and Fig. 5(c). Any physical failure is not found in top view SEM and cross sectional TEM images of cell capacitor using cross DPT. Electrical Characteristics of Memory Cell Capacitor using Double Patterning Technology : Fig. 6 shows the capacitance of cell capacitor using DPT according to capacitor height. Measured capacitance of cell capacitor using DPT is improved up to ~10% compared to calculated capacitance of cell capacitor using SET. Because the cell capacitor using cross DPT shows more rectangular shape than that of SET, surface area of cell capacitor using cross DPT is enlarged compared to that of SET. Fig. 7 shows the capacitance and breakdown voltage of capacitor using DPT. Capacitance of capacitor using cross DPT is 15fF/cell and breakdown voltage of capacitor is 2.4V. Fig. 8 shows leakage current of cell capacitor using cross DPT according to applied voltage. A breakdown voltage at 1fA/cell leakage current for cell capacitor using cross DPT is ~2.0V. That is similar to breakdown voltage of capacitor using SET. Therefore memory cell capacitor using cross DPT exhibited a capacitance enhancement value of ~10% without any decrease in breakdown voltage and leakage current. Conclusions : Memory cell capacitor using cross DPT was successfully developed for the first time. Cross DPT was introduced to overcome overlay problem of conventional DPT. Memory cell capacitor using cross DPT showed more rectangular shape without any physical failure and