Junichiro Makino, Kei Hiraki, Mary Inaba
2007 Proceedings of the 2007 ACM/IEEE conference on Supercomputing - SC '07  
We describe the GRAPE-DR (Greatly Reduced Array of Processor Elements with Data Reduction) system, which will consist of 4096 processor chips each with 512 cores operating at the clock frequency of 500 MHz. The peak speed of a processor chip is 512Gflops (single precision) or 256 Gflops (double precision). The GRAPE-DR chip works as an attached processor to standard PCs. Currently, a PCI-X board with single GRAPE-DR chip is in operation. We are developing a 4chip board with PCI-Express
more » ... , which will have the peak performance of 1 Tflops. The final system will be a cluster of 512 PCs each with two GRAPE-DR boards. We plan to complete the final system by early 2009. The application area of GRAPE-DR covers particle-based simulations such as astrophysical many-body simulations and molecular-dynamics simulations, quantum chemistry calculations, various applications which requires dense matrix operations, and many other compute-intensive applications.
doi:10.1145/1362622.1362647 dblp:conf/sc/MakinoHI07 fatcat:5w5ogh4po5bdxp4uzi4aif3ese