Leveraging reconfigurability to raise productivity in FPGA functional debug

Z. Poulos, Yu-Shen Yang, J. Anderson, A. Veneris, Bao Le
2012 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
We propose new hardware and software techniques for FPGA functional debug that leverage the inherent reconfigurability of the FPGA fabric to reduce functional debugging time. The functionality of an FPGA circuit is represented by a programming bitstream that specifies the configuration of the FPGA's internal logic and routing. The proposed methodology allows different sets of design internal signals to be traced solely by changes to the programming bitstream followed by device reconfiguration
more » ... d hardware execution. Evidently, the advantage of this new methodology vs. existing debug techniques is that it operates without the need of iterative executions of the computationally-intensive design re-synthesis, placement and routing tools. In essence, with a single execution of the synthesis flow, the new approach permits a large number of internal signals to be traced for an arbitrary number of clock cycles using a limited number of external pins. Experimental results using commercial FPGA vendor tools demonstrate productivity (i.e. run-time) improvements of up to 30× vs. a conventional approach to FPGA functional debugging. These results demonstrate the practicality and effectiveness of the proposed approach.
doi:10.1109/date.2012.6176481 dblp:conf/date/PoulosYAVL12 fatcat:mkqewn5nc5blrab4dcg2la4nh4