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A novel genetic algorithm for the automated design of performance driven digital circuits
Proceedings of the 2000 Congress on Evolutionary Computation. CEC00 (Cat. No.00TH8512)
The authors present a genetic algorithm for the design of high performance arithmetic circuits for evolvable hardware applications. A distinct feature of the algorithm is its ability to directly evolve and evaluate circuits in a hardware description language (HDL), within a novel environment termed the Virtual Chip. Because the Virtual Chip evolves circuit structures within a HDL, detailed simulation and analysis of each circuit is possible with any technology specific component library. Thisdoi:10.1109/cec.2000.870353 fatcat:yyeh7dyjcrghrm54ia6ex26p3m