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Pattern Based Cache Coherency Architecture for Embedded Manycores
2016
Procedia Computer Science
Modern parallel programming frameworks like OpenMP often rely on shared memory concepts to harness the processing power of parallel systems. But for embedded devices, memory coherence protocols tend to account for a sizable portion of chip's power consumption. This is why any means to lower this impact is important. Our idea for this issue is to use the fact that most of usual workloads display a regular behavior with regards to their memory accesses to prefetch the relevant memory lines in
doi:10.1016/j.procs.2016.05.481
fatcat:7znxuor2lffw7djjufvrganosu