Composing symbolic trajectory evaluation results [chapter]

Scott Hazelhurst, Carl-Johan H. Seger
1994 Lecture Notes in Computer Science  
Symbolic trajectory evaluation shows much promise as a method for verifying large scale VLSI designs with a high degree of automation. However, to verify today's designs, a method for composing partial verification results is needed. Consequently, we have proven a number of inference rules for the composition of symbolic trajectory evaluation results and developed a specialised theorem prover designed specifically for combining verification results based on trajectory evaluation. In the paper
more » ... discuss the underlying inference rules of the prover as well as more practical issues regarding the user interface. We conclude with an example in which we verify a design that could not have been verified directly. In particular, the complete verification of a 64 bit multiplier takes under 15 minutes on a Sparc 10/51 machine.
doi:10.1007/3-540-58179-0_61 fatcat:y6vpfsuthrbd3mho3qj5uwxcc4