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A 65 nm 0.165 fJ/Bit/Search 256$\,\times\,$144 TCAM Macro Design for IPv6 Lookup Tables
2011
IEEE Journal of Solid-State Circuits
Ternary content addressable memory (TCAM) is extensively adopted in network systems. As routing tables become larger, energy consumption and leakage current become increasingly important issues in the design of TCAM in nano-scale technologies. This work presents a novel 65 nm energy-efficient TCAM macro design for IPv6 applications. The proposed TCAM employs the concept of architecture and circuit co-design. To achieve an energy-efficient TCAM architecture, a butterfly match-line scheme and a
doi:10.1109/jssc.2010.2082270
fatcat:vbyzjmzcwfalbkaaaerzj7qpgu