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ME64 - A Parallel Hardware Architecture for Motion Estimation Implemented in FPGA
[chapter]
IFIP International Federation for Information Processing
Key words: Digital video compression is a computationally intensive task, in which motion estimation accounts for a significant portion of the arithmetic operations. This paper presents ME64, a dedicated scalable hardware architecture for fast computation of motion vectors. ME64 is a highly parallel architecture, based on a matrix of 64 processing elements at its core, an I/O interface, and comparison and control units. The proposed architecture was implemented in an FPGA to treat reference and
doi:10.1007/1-4020-8149-9_32
dblp:conf/ifip10-3/ZandonaiBB04
fatcat:tizz5li6rzdw5bkl7fno5w7hrq