The impact of out-of-order commit in coarse-grain, fine-grain and simultaneous multithreaded architectures

R. Ubal, J. Sahuquillo, S. Petit, P. Lopez, J. Duato
<span title="">2008</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="" style="color: black;">Proceedings, International Parallel and Distributed Processing Symposium (IPDPS)</a> </i> &nbsp;
Multithreaded processors in their different organizations (simultaneous, coarse grain and fine grain) have been shown as effective architectures to reduce the issue waste. On the other hand, retiring instructions from the pipeline in an out-of-order fashion helps to unclog the ROB when a long latency instruction reaches its head. This further contributes to maintain a higher utilization of the available issue bandwidth. In this paper, we evaluate the impact of retiring instructions out of order
more &raquo; ... on different multithreaded architectures and different instruction fetch policies, using the recently proposed Validation Buffer microarchitecture as baseline out-of-order commit technique. Experimental results show that, for the same performance, out-of-order commit permits to reduce multithread hardware complexity (e.g., fine grain multithreading with a lower number of supported threads). VB-MT Microarchitecture Providing Multithreading support As in any multithreading model, the VB-MT architecture provides the illusion of having various logical processors, that is, various simultaneously active software contexts, one per hardware thread. Although most hardware structures
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="">doi:10.1109/ipdps.2008.4536284</a> <a target="_blank" rel="external noopener" href="">dblp:conf/ipps/UbalSPLD08</a> <a target="_blank" rel="external noopener" href="">fatcat:evycgvofdfaljoxaqsjhcqwnim</a> </span>
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