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Statistical timing analysis using bounds [IC verification]
2003 Design, Automation and Test in Europe Conference and Exhibition
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to the dependencies created by reconverging paths in the circuit. In this paper, we propose a new approach to statistical timing analysis which uses statistical bounds. First, we provide a formal definition of the statistical
doi:10.1109/date.2003.1253588
fatcat:3ls3k62elvfl7h5yimwm3uq3wi