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We present a dictionary-based test data compression approach for reducing test data volume in SOCs. The proposed method is based on the use of a small number of ATE channels to deliver compressed test patterns from the tester to the chip and to drive a large number of internal scan chains in the circuit under test. Therefore, it is especially suitable for a reduced pin-count and lowcost DFT test environment, where a narrow interface between the tester and the SOC is desirable. Thedoi:10.1145/944027.944032 fatcat:fn55pasczbeprptntyfynqy34q