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Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477)
In this paper, we propose a framework for low-energy digital signal processing (DSP) where the supply voltage is scaled beyond the critical voltage required to match the critical path delay to the throughput. This deliberate introduction of input-dependent errors leads to degradation in the algorithmic performance, which is compensated for via algorithmic noise-tolerance (ANT) schemes. The resulting setup that comprises of the DSP architecture operating at sub-critical voltage and the errordoi:10.1109/lpe.1999.799405 fatcat:aprbecc5drh77pogrzcj47jwkm