Collection of high-level microprocessor bugs from formal verification of pipelined and superscalar designs

M.N. Velev
International Test Conference, 2003. Proceedings. ITC 2003.  
The paper presents a collection of 93 different bugs, detected in formal verification of 65 student designs that include: 1) singleissue pipelined DLX processors; 2) extensions with exceptions and branch prediction; and 3) dual-issue superscalar implementations. The processors were described in a high-level HDL, and were formally verified with an automatic tool flow. The bugs are analyzed and classified, and can be used in research on microprocessor testing.
doi:10.1109/test.2003.1270834 dblp:conf/itc/Velev03 fatcat:fp7e64dtf5f7toekqx4n77ig2m