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International Journal of Recent Trends in VLSI
Caches are most vulnerable to the transient errors. It is important to prevent transient errors and provide a correction mechanism for hardware circuits. To prevent transient errors, cache memories employ error protection mechanisms, such as parity codes and single-bit error correction and double-bit error detection codes. These schemes are not efficient in terms of area overhead and error protection coverage. So another method is proposed to exploit same tag bits to improve error protectionfatcat:4wucymsuzbfadfx43j7o7plaqm