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Modelling bus contention during system early design stages
2017
2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)
Reliably upperbounding contention in multicore shared resources is of prominent importance in the early design phases of critical real-time systems to properly allocate time budgets to applications. However, during early stages applications are not yet consolidated and IP constraints may prevent sharing them across providers, challenging the estimation of contention bounds. In this paper, we propose a model to estimate the increase in applications' execution time due to on-chip bus sharing when
doi:10.1109/sies.2017.7993393
dblp:conf/sies/TrillaHAC17
fatcat:m42w4gvl55gezkscqiahvu3raa