A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf
.
Techniques for yield enhancement of VLSI adders
Proceedings The International Conference on Application Specific Array Processors
For VLSI application-specific a m y s and other regular VLSI circuits, two techniques are available for yield enhancement, namely defect-tolerance and layout modifications. In this paper, we compare these two yield enhancement appruaches by using adders as an ezample. Our yield projections indicate that the layout modification technique is more eficient when the defect density is low, while reconjiguration is more eficient for a high defect density. However, f" the point of the view of
doi:10.1109/asap.1995.522926
dblp:conf/asap/ChenK95
fatcat:xeoxl6t4mnegxpjdeug33bumke