Techniques for yield enhancement of VLSI adders

Zhan Chen, I. Koren
Proceedings The International Conference on Application Specific Array Processors  
For VLSI application-specific a m y s and other regular VLSI circuits, two techniques are available for yield enhancement, namely defect-tolerance and layout modifications. In this paper, we compare these two yield enhancement appruaches by using adders as an ezample. Our yield projections indicate that the layout modification technique is more eficient when the defect density is low, while reconjiguration is more eficient for a high defect density. However, f" the point of the view of
more » ... yield, the layout modification is superior to defect tolerance in the practical range of defect density.
doi:10.1109/asap.1995.522926 dblp:conf/asap/ChenK95 fatcat:xeoxl6t4mnegxpjdeug33bumke