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Dynamically managing the communication-parallelism trade-off in future clustered processors
2003
Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03
Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-delay-constrained process technologies. As increasing transistor counts allow an increase in the number of clusters, thereby allowing more aggressive use of instructionlevel parallelism (ILP), the inter-cluster communication increases as data values get spread across a wider area. As a result of the emergence of this
doi:10.1145/859618.859650
fatcat:65mb7apno5ajxkwevbozfjbnki