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Duet: an accurate leakage estimation and optimization tool for dual-V/sub t/ circuits
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
We present a new approach for the estimation and optimization of standby power dissipation in large MOS digital circuits. We first introduce a new approach for accurate and efficient calculation of the average standby or leakage current in large digital circuits by introducing the concepts of "dominant leakage states" and the use of state probabilities. Combined with graph reduction techniques and simplified nonlinear simulation, our method achieves speedups of three to four orders of magnitudedoi:10.1109/92.994980 fatcat:auf3ac57c5h67b6navmlflc4zi