A robust synchronizer

Jun Zhou, D. Kinniment, G. Russell, A. Yakovlev
2006 IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)  
We describe a new latch circuit designed to give a high performance in low voltage synchronizer applications. By increasing the latch current only during metastability, we can more than maintain the value of the metastability time constant, τ, without significantly increasing the power. Our circuit also reduces the variation of τ with Vdd and temperature, so that it has a lower τ at 50% Vdd than the conventional jamb latch has at 60% Vdd. References
doi:10.1109/isvlsi.2006.12 dblp:conf/isvlsi/ZhouKRY06 fatcat:dst4q75lnvfi5c2ncv6z6ouxvm