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Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers
2013
2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS)
Three-dimensional stacked integrated circuits (3D-SICs) implemented with through-silicon vias (TSVs) and micro-bumps open new horizons for faster, smaller, and more energy-efficient chips. As all micro-electronic structures, these 3D chips and their interconnects need to be tested for manufacturing defects. Previously, we defined, implemented, and automated a 3D-DfT (Design-for-Test) architecture that provides modular test access for 3D-SICs containing monolithic logic dies in a single-tower
doi:10.1109/ets.2013.6569350
dblp:conf/ets/PapameletisKCMH13
fatcat:ln36ida2tvanfiz7h6xlnuxxhi