Lattice adaptive filter implementation for FPGA

Zdenek Pohl, Rudolf Matoušek, Jirí Kadlec, Milan Tichý, Miroslav Lícko
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
The employment of field programmable gate arrays (FPGAs) to a robot controller is very attractive, since it allows for fast IC prototyping and low cost modifications. The speedup is achieved because of pipelining and dedicated functions in hardware that are customized to the problem. The self learning ability and the adaptive nature of an Artificial Neural Network (ANN) makes it a good candidate for the control structure of a robot's navigation. An evolutionary approach in designing robots can
more » ... volve the architecture of ANNs and yields automatic creation of the controller while the robot moves in task environments. The poster briefly describes the important hardware issues involved with the FPGA based design of an evolutionary robot controller for the collision free navigation of mobile robots In code division multiple access (CDMA) systems the base station identifies each user in a cell by unique orthogonal (Walsh) codes. The Walsh codes are generated at the transmitter using a Walsh-Hadamard function. A Fast Hadamard Transformer (FHT) is used at the receiver to decode the transmitted codes. The purpose of this study is to design a FHT which utilizes less hardware resources as compared to the existing designs and also suggest means for reducing the input length of the Walsh sequence. Our study results indicate that the FHT design using 16-chip sequence achieves 90% reduction in hardware resources (equivalent gate count) as compared to the design which uses 256-chip sequence. Also, the maximum frequency of operation of the 16-chip FHT (35.679 MHz) is more than double as compared to the 256-chip FHT (16.025 MHz). Applications such as digital cell phones, 3G wireless receivers, and voice over IP, require DSP functions that are typically mapped onto general purpose DSP processors. With the introduction of advanced FPGA architectures which provide built-in DSP support such as the Xilinx Virtex-II, and the Altera Stratix, a new hardware alternative is available for DSP designers. DSP design has traditionally been divided into algorithm development and hardware/software implementation. The majority of DSP algorithm developers use the MATLAB language for prototyping their DSP algorithm. Hardware design teams take the specifications in MATLAB code and manually create an RTL model in VHDL or Verilog. This paper describes how area-performance tradeoffs can be performed quickly at the high-level using a behavioral synthesis tool called AccelFPGA which reads in highlevel descriptions of DSP applications written in MATLAB, and automatically generates synthesizable RTL models in VHDL or Verilog. Experimental results are reported with the AccelFPGA compiler on a set of 8 MATLAB benchmarks that are mapped onto the Xilinx Virtex II and Altera Stratix FPGAs.
doi:10.1145/611817.611877 dblp:conf/fpga/PohlMKTL03 fatcat:vg523unfzvcmvl2rsw4ja3ksma