Profiling tools for hardware/software partitioning of embedded applications

Dinesh C. Suresh, Walid A. Najjar, Frank Vahid, Jason R. Villarreal, Greg Stitt
2003 SIGPLAN notices  
Loops constitute the most executed segments of programs and therefore are the best candidates for hardware software partitioning. We present a set of profiling tools that are specifically dedicated to loop profiling and do support combined function and loop profiling. One tool relies on an instruction set simulator and can therefore be augmented with architecture and microarchitecture features simulation while the other is based on compile-time instrumentation of gcc and therefore has very
more » ... e slow down compared to the original program We use the results of the profiling to identify the compute core in each benchmark and study the effect of compile-time optimization on the distribution of cores in a program. We also study the potential speedup that can be achieved using a configurable system on a chip, consisting of a CPU embedded on an FPGA, as an example application of these tools in hardware/software partitioning.
doi:10.1145/780731.780759 fatcat:kcwibnuntjhedmg3bvqoot7ame