12Gbps SerDes Jitter Tolerance BIST in production loopback testing with enhanced spread spectrum clock generation circuit

Yi Cai, Liming Fang, Ivan Chan, Max Olsen, Kevin Richter
2013 2013 IEEE International Test Conference (ITC)  
We designed and tested an on-chip BIST test for high speed SerDes devices. Jitter Tolerance testing is a critical way to stress the SerDes receivers. A jitter free loopback test hardly represents the real application environment. We implemented a jitter injection technique to precisely injecting the amount of in-band and out-of-band jitter to effectively testing receiver clock and data recovery circuits (CDR). Because out-of-band jitter is more effective in stressing the CDR, it is critical to
more » ... it is critical to generate jitter frequency that is higher than the receiver CDR loop bandwidth. Both the jitter frequency and amplitude can be programmed digitally in this BIST implementation. And more importantly, it does NOT require any external instrument for calibration. As a result, overall production test coverage is enhanced without additional test cost and tester instrument calibration hardware.
doi:10.1109/test.2013.6651882 dblp:conf/itc/CaiFCOR13 fatcat:oq7yhlpcfbdrhkwkaicviorg4e