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The next generation UltraSPARC-I CPU represents a significant step forward in processor performance at the cost of increased design complexity. Added complexity increases the risks in achieving functionally correct first silicon. Existing design verification techniques were supplemented by applying emulation to obtain an early look at functionality. Discussed are the goals, methods and results of the UltraSPARC-I emulation. 32nd ACM/IEEE Design Automation Conference ®doi:10.1145/217474.217483 dblp:conf/dac/GateleyBCCDDEFGGJKKMNNOPSSWW95 fatcat:zgrrbfbvpvhf7hq2huqhwi7njy