Impact Of Process Variations On The Vertical Silicon Nanowire Tunneling Fet (Tfet)

Z. X. Chen, T. S. Phua, X. P. Wang, G. -Q. Lo, D. -L. Kwong
2013 Zenodo  
This paper presents device simulations on the vertical silicon nanowire tunneling FET (VSiNW TFET). Simulations show that a narrow nanowire and thin gate oxide is required for good performance, which is expected even for conventional MOSFETs. The gate length also needs to be more than the nanowire diameter to prevent short channel effects. An effect more unique to TFET is the need for abrupt source to channel junction, which is shown to improve the performance. The ambipolar effect suppression
more » ... y reducing drain doping concentration is also explored and shown to have little or no effect on performance.
doi:10.5281/zenodo.1087776 fatcat:7erzdasfjjh3fegjjaizqecxzm