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Low Latency Scheduling Algorithm for Shared Memory Communications over Optical Networks
2013
2013 IEEE 21st Annual Symposium on High-Performance Interconnects
Optical Network on Chips (NoCs) based on silicon photonics have been proposed to reduce latency and power consumption in future chip multi-core processors (CMP). However, high performance CMPs use a shared memory model which generates large numbers of short messages, typically of the order of 8-256B. Messages of this length create high overhead for optical switching systems due to arbitration and switching times. Current schemes only start the arbitration process when the message arrives at the
doi:10.1109/hoti.2013.14
dblp:conf/hoti/MadarbuxLW13
fatcat:do6jdprfbra47npum24rqrfofa