Spur-Suppression Techniques for Frequency Synthesizers

Che-Fu Liang, Hsin-Hua Chen, Shen-Iuan Liu
2007 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
A frequency synthesizer with two spur-suppression circuits has been fabricated in 0.18 um CMOS technology. The chip area is 1.3 mm 1.3 mm. The frequency synthesizer consumes 18.9 mW from a 1.8-V supply. Compared with the conventional frequency synthesizer without the spur-suppression circuit, the measured reference spur at 8 MHz is reduced by 18 dBc for the first spur-suppression circuit and 31 dBc for the second one. The measured switching time from 1792 to 1824 MHz is 27.89 us within 20 ppm of the target frequency.
doi:10.1109/tcsii.2007.896938 fatcat:dehnduthfng5zlvz5sp63w3uha