Bit Swapping and Cell Ordering on Finding Faults in Test Pattern Generation using BIST
International Journal for Research in Applied Science and Engineering Technology
Testing for delay and stuck-at faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) schemes are attractive for such comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In the proposed work, necessary and sufficient conditions to ensure complete/ maximal pattern-pair coverage for sequential circuit has been derived. A new low power weighted pseudorandom test pattern
... or using weighted test-enable signals is proposed using a new clock disabling scheme .It supports both pseudorandom testing and deterministic BIST. To implement the low power BIST scheme, a design-for-testability (DFT) architecture is presented. During the pseudorandom testing phase, an LP weighted random test pattern generation scheme is used by disabling a part of scan chains.A novel low-power bit-swapping LFSR (BS-LFSR) is used to minimize the transistions, while keeping the randomness almost similar. The BS-LFSR is combined with a scan-chain-ordering algorithm that orders the cells in a way that reduces the average and peak power (scan and capture) in the test cycles (or) while scanning out a response to a signature analyzer. These techniques have a substantial effect on average and peak power compared to the existing approach.