Design of Power Efficient Dynamic Latch Comparator for High Resolution SAR ADCs

G. Senthil Kumar
2019 International Journal of Research in Advent Technology  
In today's high performance low power era, there is an increasing demand for a power efficient comparators with high accuracy at moderate conversion speed for ADC, DAC and bio-potential acquisition system applications. This paper presents the design of power efficient dynamic latch comparator using inverter based preamplifier to overcome offset errors for enhancing the performance. The technique along with preamplifier using inverter topology limits the noise against inaccuracy issues like
more » ... m offset errors and quantization error by reducing the common mode input voltage, V cm and also, preserves the power efficiency when extending the effective number of bits (ENOB) bits for high resolution ADCs. The simulation is performed using 180nm CMOS process technology in Mentor Graphics. Proposed dynamic latch comparator outperforms the conventional dynamic comparators in terms of low power consumption with high resolution for ADCs.
doi:10.32622/ijrat.74201947 fatcat:vsidxcdsmfhzvhdyr5f242fw4m