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The number of instructions a processor's instruction queue can examine (depth) and the number it can issue together (width) determine its ability to take advantage of the ILP in an application. Unfortunately, increasing either the width or depth of the instruction queue is very costly due to the content-addressable logic needed to wakeup and select instructions out-of-order. This work makes the observation that a large number of instructions have both operands ready at dispatch, and thereforedoi:10.23919/date.2019.8715034 dblp:conf/date/Alipour0KB19 fatcat:saomqfdwxnhshder2lbyucf6ti