This letter presents a fully integrated on-chip digital mismatch compensation system for time-based time-interleaved data converters. The proposed digital compensation features blind calibration of gain, offset, and timing mismatches. The implemented system uses time-based sampling clock mismatch detection achieving convergence within 32K samples, which is on par with analog-assisted background methods. A specialized filter structure compensates for timing mismatches of magnitude up to 0.21 of

more »

... he sampling period, nearly triple the range of other published digital compensation methods, and is effective for input signals up to 0.92 Nyquist bandwidth. The on-chip digital correction achieves suppression of all mismatch tones to levels below -60 dBc while running fully in background. The operation is demonstrated with an 8x time-interleaved 2-GS/s ADC prototype chip implemented in a 28-nm CMOS process. Index Terms-time-interleaving, mismatch, digital calibration, time-based, analog-to-digital converter (ADC), cyclic-coupled ring oscillator (CCRO), timing skew, least mean squares (LMS), finite impulse response (FIR). I. INTRODUCTION M ODERN wireless communication applications require analog-to-digital converters (ADC) with gigahertz range bandwidth (BW). The time-interleaved (TI) ADC is a common architecture for achieving wideband operation by carrying out the conversion with several parallel sub-ADCs. However, the overall performance of the TI-ADC is limited by the matching between the sub-ADCs in terms of gain, offset and timing. The mismatches can be detected and corrected in analog, digital or mixed-signal domains. Analog-assisted digital methods can provide fast and accurate calibration for the mismatch errors. However, they require auxiliary circuits [1], [2] or reference ADCs. Split TI-ADC is proposed for reference-free calibration [3] . Fully digital methods [4] can provide more general and flexible solutions that are portable between process nodes and designs. This paper presents a fully integrated on-chip digital mismatch compensation solution with a unique background skew correction scheme facilitated by the time-based converter architecture. It employs a least-mean-square (LMS) algorithm for blind gain and offset calibration and a fully digital skew mismatch estimator, achieving convergence within 32K samples, which is comparable to other analog-assisted methods. Furthermore, a cascaded reconstruction filter structure is implemented to compensate for timing mismatches of magnitude VTC Encoder