The implementation of a comparator (1-bit) circuit using a MUX-6T based full adder cell is designed with a combination of multiplexing control input and Boolean identities. The proposed comparator design features a higher computing speed and lower energy consumption due to the efficient MUX-6T adder cell. The design adopts multiplexing technique with control input to alleviate the threshold voltage loss problem which is commonly encountered in Pass Transistor Logic (PTL) design. The design

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... sed successfully embeds the buffering circuit in the full adder design which helps the cell to operate at lower supply voltage compared with the other related existing designs. It also enhances the speed of the cascaded operation significantly while maintaining the performance edge in energy consumption. In this design the transistor count is minimized. For performance comparison, the proposed MUX-6T comparator is compared with existing full adder based comparator using cadence tool. The simulations are performed for 45nm and 90nm technologies; indicate that the proposed design has the lowest energy consumption along with the performance edge on both speed and energy.