Custom Instruction Integration Method within Reconfigurable SoC and FPGA Devices
2006 International Conference on Microelectronics
General-purpose processors that are utilized as utilize an ASIC, it must be specially rewritten to do so. cores are often incapable of achieving the challenging cost, Rewriting system applications or few tasks of applications can performance, and power demands of high-performance audio, be a large engineering burden. For this reason, the use of video, and networking applications. To meet these demands, reusable components libraries is encouraged to accelerate the most systems employ a number of
... hardware accelerators to offdesign process and to conserve the compatibility for the load the computationally demanding portions of the application. evolution in system on chip (SoC design. As an alternative to this strategy, we examine customizing the computation capabilities of a core processor for a particular ap-Adding custom hardware In processor core Is another method plication. Our goal is to generate a prototype of reconfigurable for providing enhanced performance in SoC. In general, the custom instruction SoC to answer application request using critical portions of an application's data flow graph (DFG) can FPGA technology. To give more flexibility to system, we be accelerated by mapping them to a custom hardware. Usually, addressed customized core with coarse and finite granularity. In there are two granularity levels to add dedicated hardware to this paper, we provide an overview of a method to identify coarse processor core system: instruction granularity level and function and finite grain instruction set extensions in application code and granularity level. The instruction granularity consists in linking integration process in reconfigurable SoC based on NIOSII custom hardware with the main registers of processor core and a processor core. 3D synthesis application was proposed as a case custom instruction opcode is added to the processor instruction study for experimentation. set. The number of custom instructions depends on the processor core capacity, for example ARM core provides 16 I. INTRODUCTION custom instruction extensions. The function granularity consists in adding the custom hardware as a slave or a master peripheral using bus communication. In this case one instruction extension common method for providing performance improvement can not drive the functionality between the processor and the for an embedded computer system is to create customized customized peripheral. So in many cases, specific subroutines hardware solutions for particular tasks. For example, should be coded to control the custom hardware activity and the embedded computer system often has one or more application communication with the processor core. The number of added specific integrated circuits (ASICs) to perform computationally hardware functions depends on the bus bandwidth and the demanding tasks. ASICs are very effective at improving device size in the case of FPGA circuits. In the case of performance, typically yielding several orders of magnitude instruction granularity the processor is in hold mode and it is speedup along with reduced energy consumption. blocked in custom instruction execution, but in function Unfortunately, there are also negative aspects to using ASICs. granularity the mutual execution of processor core and custom The primary problem is that ASICs only provide a dedicated peripheral is possible. hardwired architecture solution, meaning that only a limited In this paper we are interested to custom instruction integration number of applications will be able to fully explore the ASIC in reconfigurable system on chip. We propose a method to architecture. If an application changes, because of a fixed bug or identify the parts of application code that should be executed as a change in standards, the system will usually no longer be able custom instructions. Then, we present the integration process of to take advantage of the ASIC device architecture. So, custom instructions within NIOSII processor core. 3D frame reconfigurable feature was introduced in embedded system synthesis application is used as an experimentation case study. concept as a need to solve bugs and to support the evolution of The paper is organized as follows. In Section 1 we discuss the related work in custom instruction design. Section 2 presents I -t44-07(. -g0(2 OAO 0 © 6 IEEER 131 Authorized licensed use limited to: UNIVERSITE DE BRETAGNE SUD. Downloaded on July 28, 2009 at 08:26 from IEEE Xplore. Restrictions apply.