A Many-Core Parallelizing Processor

Katarzyna Porada
2017 2017 International Conference on High Performance Computing & Simulation (HPCS)  
This paper presents a new many-core processor design to parallelize by hardware. The parallel run is built from a deterministic parallelization of the sequential trace, hence inheriting its order. The code pieces are distributed according to the sequential order in a way which favors neighbor cores communications. The ordered placement simplifies the processor interconnect and the memory sharing. The paper presents a VHDL implementation of a 64-core version of the processor. The synthesized
more » ... otype proves that the automatic parallelization technique works and the speed and size of the synthesis show that the design is scalable. Keywords-many-core processor, out-of-order processor, parallelizing processor, determinism, VHDL prototype I.
doi:10.1109/hpcs.2017.133 dblp:conf/ieeehpcs/Porada17 fatcat:ew2q4hs4fjezdkerlkrizr7pke