A hybrid wave-pipelined network router

J.G. Delgado-Frias, J. Nyathi
Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems  
In this paper a novel hybrid wave-pipelined bitpattern associative router is presented. A router is an important component in communication network systems. The bit-pattern associative router (BPAR) allows for flexibility and can accommodate a large number of routing algorithms. In this study a hybrid wave-pipelined approach has been proposed and implemented. Hybrid wave-pipelining allows for the reduction of the delay difference between the maximum and minimum delays by narrowing the gap
more » ... owing the gap between each stage of the system. This approach yields narrow "computing cones" that could allow faster clocks to be run. This is the first study in wave-pipelining that deals with a system that has substantially different pipeline stages. The bit-pattern associative router has three stages: condition match, selection function, and port assignment. In each stage data delay paths are tightly controlled in order to optimize the proper propagation of signals. Internal control signals are generated to ensure that data propagates between stages in a proper fashion. Results from our study show that using a hybrid wave-pipelining significantly reduces the clock period. The hybrid wave pipelined system described in this paper has been fabricated using a 0.5 m technology. Index Terms-Hybrid wave-pipelining, wave-pipelined clock, bitpattern associative memory, dynamic ternary content addressable memory, computer network address decoder, delay balancing.
doi:10.1109/iwv.2001.923156 fatcat:5q634k5dybeinnox5ihrsgv5qu