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A low power charge-recycling ROM architecture
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)
A new low power charge recycling ROM (CR-ROM) architecture is proposed. The CR-ROM uses charge-recycling method [4] in bit lines of ROM to save the power consumption. About 90% of the total power used in the ROM is consumed in bit lines [1] . With the proposed method, power consumption in ROM bit lines can be reduced asymptotically to zero if the number of bit lines is infinite and the sense amplifiers detect infinitely small voltage difference. However, the real sense amplifiers cannot sense
doi:10.1109/iscas.2001.922286
dblp:conf/iscas/YangK01
fatcat:xm7k2r2ogfgdvdvstlc5evf2gu