Designer-in-the-loop recoding of ESL models using static parallel access conflict analysis

Xu Han, Weiwei Chen, Rainer Dömer
2013 Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems - M-SCOPES '13  
At the Electronic System Level (ESL), a well-defined design model enables early design space exploration and automatic synthesis on custom multiprocessor platforms. However, the initial design model is usually manually recoded from unstructured and sequential source code. To efficiently create cleanly structured and parallel models, this paper proposes a designer-in-the-loop approach on Eclipse platform where the system model is analyzed and recoded using automated functions. Particularly,
more » ... ced static analysis at compile time can guarantee that the parallelism in the model is safe and free from race conditions. Experiments using the tool with a class of graduate students show significant productivity gains and error reduction in model creation.
doi:10.1145/2463596.2463599 dblp:conf/scopes/HanCD13 fatcat:4pn2aezogfhrzho7tkuzgk222q