A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2007; you can also visit the original URL.
The file type is
Wire delay is rapidly becoming a major bottleneck in reconfigurable systems, creating a significant gap between the clock rates of reconfigurable logic and custom circuits. In this paper, we describe the design of the reconfigurable clusters on the Amalgam clustered programmable-reconfigurable processor. Amalgam's reconfigurable clusters are divided into four segments of reconfigurable logic, limiting the length of individual wires in the cluster. They support pipelining of wire delays bydoi:10.1016/j.micpro.2006.03.001 fatcat:izat3z4hdrfg3lzeyapmr44e5y