We present an analysis of electrical noise in III-V heterojunction TFET (HTFET). Using numerical simulations, random telegraph noise (RTN) amplitude induced by a single charge trap is investigated with regard to trap location, electron band-to-band-generation rate, bias, and transistor size. It is found that HTFET RTN amplitude does not scale inversely with gate length and is governed by tunneling distance of carriers at source-channel junction. HTFET exhibits 40% less relative RTN amplitude at

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... 0.3 V at gate lengths around 20 nm, over subthreshold Si-FinFET. RTN of HTFET at V GS = 0 V is higher for a trap location at source-channel tunnel junction. To analyze flicker, shot, and thermal noise, we created transistor level Verilog-A-based electrical noise models. The results indicate HTFETs competitive noise performance in megahertz frequency range, over Si-FinFET. In the range 10 GHz or more with operating voltages exceeding 0.3 V, HTFET input noise is worse due to the dominance of shot noise. A differential amplifier with active load is used to examine the electrical noise performance at circuit level. We emphasize that high intrinsic gain, drive current, and output resistance of HTFET can be used to achieve superior mixed signal performance metrics in HTFET design over Si-FinFET design, at an improved electrical noise performance. Index Terms-Electrical noise, flicker, heterojunction TFET (HTFET), random telegraph noise (RTN), shot, Technology Computer Aided Design (TCAD) simulation, thermal, trap, Verilog-A-based model.