A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf
.
Core-Selectability in Chip Multiprocessors
2009
2009 18th International Conference on Parallel Architectures and Compilation Techniques
The centralized structures necessary for the extraction of instruction-level parallelism (ILP) are consuming progressively smaller portions of the total die area of chip multiprocessors (CMP). The reason for this is that scaling these structures does not enhance general performance as much as scaling the cache and interconnect. However, the fact that these structures now consume less proportional die area opens an avenue to enhancing their performance through truly overcoming the
doi:10.1109/pact.2009.44
dblp:conf/IEEEpact/Najaf-abadiCR09
fatcat:qvlgvgvhdrd5rkxh23xatavjv4