Ultra-Low Power and Reliable SRAM for Systems-on-Chip
Harsh Naranbhai Patel
The number of ubiquitous sensors has increased to more than double the human population and is expected to continue growing in the future. The pervasive use of sensors for applications such as personal healthcare and the Internet of Things (IoT) presents a growing sustainability challenge concerning the availability and accessibility of power sources. With 50 billion devices expected to be connected to the Internet by 2020, recharging or replacing batteries at a regular interval will result in
... normous time and cost overhead due to the restricted growth of batteries. Therefore, the need for the self-powered systems is being researched as an alternative solution to operate at scaled supply voltage below its threshold voltage to minimize an active power (CV 2 DD ). The important metrics for such applications change from the traditional performance-driven to low-energy (i.e., longer battery life) and reliability. To address these challenges, it has become critical to re-evaluate the different design decisions made under high-performance requirements and to revalidate any different trade-offs among the metrics under consideration. While analyzing the major contributors for power dissipation in present state-of-the-art low-power ICs, it has been found that Static Random Access Memory (SRAM) consumes almost 65% of the total chip power. Therefore, designing an SRAM to operate in the subthreshold region of operation provides an opportunity for reducing the overall power dissipation in such low-power ICs. However, the SRAM functionality in the sub-threshold operation becomes extremely sensitive to the process and temperature variations, and other environmental conditions such as radiation-induced soft errors. As a result of these factors, the power reduction and robustness become major challenges for the subthreshold design targeting ULP platforms. In this work, we present various circuits and architectural techniques to enable ULP and reliable SRAMs to optimize energy per operation for a complex System-on-Chip (SoC). We investigate various subthreshold SRAM design trade-offs to achieve a sub-uW battery-ii less BSN system. First, we explore different design knobs for an optimal SRAM design targeting ULP applications. These knobs include leveraging advanced fabrication technology, optimal device selection, circuit design techniques, and architectural techniques. Next, we evaluate the efficacy of different read and write peripheral assist techniques for improving reliability and energy efficiency of subthreshold SRAMs and provide stability, power, and performance trade-offs for system level optimization. The result of various optimization approaches resulted in a leakage and energy optimized SRAM operating over with leakage power reduced to 1.5 pW/bit while consuming only 6.24 pJ/access energy that is 40% more efficient than the previous version. To address a wide range of IoT applications with energy optimization, we propose a Canary sensor based minimum supply voltage (V M IN ) tracking with optimal selection of the peripheral assist techniques. Later, we address the reliability issue at subthreshold operation using a process, voltage, and temperature (PVT) variation mitigation controller. Finally, the impact of the radiation-induced soft error is evaluated to provide a comprehensive study on reliability for the ULP SRAM at scaled V DD .