Top-Gate Amorphous Silicon TFT With Self-Aligned Silicide Source/Drain and High Mobility

Yifei Huang, Bahman Hekmatshoar, Sigurd Wagner, James C. Sturm
2008 IEEE Electron Device Letters  
We report a process for top-gate amorphous silicon thin-film transistors (α-Si TFTs) that employs a self-aligned metal silicide for source and drain (S/D). All process steps, including deposition of active layers and formation of metal silicide, are accomplished at temperatures that are less than or equal to 280 • C. The thermal budget is compatible with flexible polymer substrates. The fabricated devices exhibit threshold voltages of ∼2.7 V, saturation electron field-effect mobility of 1.0 cm
more » ... /V · s, subthreshold slope of 600 mV/dec, and on/off ratio of ∼ 2 × 10 6 . These top-gate α-Si TFTs with self-aligned silicide S/D have dc performance that is comparable to that of conventional bottom-gate α-Si TFTs. Our results suggest that the top-gate α-Si TFT geometry merits reevaluation for industrial use. Index Terms-Amorphous silicon (α-Si), self-aligned silicide, thin-film transistor (TFT), top gate.
doi:10.1109/led.2008.2000645 fatcat:ezfxnkaq2zcezdqrs5lwhdni64