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Top-Gate Amorphous Silicon TFT With Self-Aligned Silicide Source/Drain and High Mobility
2008
IEEE Electron Device Letters
We report a process for top-gate amorphous silicon thin-film transistors (α-Si TFTs) that employs a self-aligned metal silicide for source and drain (S/D). All process steps, including deposition of active layers and formation of metal silicide, are accomplished at temperatures that are less than or equal to 280 • C. The thermal budget is compatible with flexible polymer substrates. The fabricated devices exhibit threshold voltages of ∼2.7 V, saturation electron field-effect mobility of 1.0 cm
doi:10.1109/led.2008.2000645
fatcat:ezfxnkaq2zcezdqrs5lwhdni64