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hls4ml: deploying deep learning on FPGAs for L1 trigger and Data Acquisition
2019
Zenodo
Machine learning is becoming ubiquitous across HEP. There is great potential to improve trigger and DAQ performance with it. However, the exploration of such techniques within the field in low latency/power FPGAs has just begun. We present hls4ml, a user-friendly software, based on High-Level Synthesis (HLS), designed to deploy network architectures on FPGAs. As a case study, we use hls4ml for boosted-jet tagging with deep networks at the LHC. We map out resource usage and latency versus
doi:10.5281/zenodo.3598988
fatcat:jaqavik2cjbkfic4q2ydho3dyq