Comparison of parallelization strategies for min-sum decoding of irregular LDPC codes

Hua Xu, Wei Wan, Wei Wang, Jun Wang, Jiadong Yang, Yun Wen
<span title="">2013</span> <i title="Tsinghua University Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/w77vm44enzh4tgk44gtrsw7f64" style="color: black;">Tsinghua Science and Technology</a> </i> &nbsp;
Low-Density Parity-Check (LDPC) codes are powerful error correcting codes. LDPC decoders have been implemented as efficient error correction codes on dedicated VLSI hardware architectures in recent years. This paper describes two strategies to parallelize min-sum decoding of irregular LDPC codes. The first implements min-sum LDPC decoders on multicore platforms using OpenMP, while the other uses the Compute Unified Device Architecture (CUDA) to parallelize LDPC decoding on Graphics Processing
more &raquo; ... its (GPUs). Empirical studies on data with various scales show that the performance of these decoding processes is improved by these parallel strategies and the GPUs provide more efficient, fast implementation decoder.
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