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The demands for high performance computing with a low cost and low power consumption are driving a transition towards multi-core processors in many consumer and industrial applications. However, the adoption of multi-core processors in the domain of real-time systems faces a series of challenges that has been the focus of great research intensity during the last decade. These challenges arise in great part from the non real-time nature of the hardware arbiters that schedule the access to shareddoi:10.4230/lipics.ecrts.2019.7 dblp:conf/ecrts/RivasGPP19 fatcat:4lfhjev62zgyhj2hyztyzmgpqa