Equivalent circuit model of on-wafer CMOS interconnects for RFICs

Xiaomeng Shi, Jian-Guo Ma, Kiat Seng Yeo, Manh Anh Do, Erping Li
2005 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
This paper investigates the properties of the on-wafer interconnects built in a 0.18-m CMOS technology for RF applications. A scalable equivalent circuit model is developed. The model parameters are extracted directly from the on-wafer measurements and formulated into empirical expressions. The expressions are in functions of the length and the width of the interconnects. The proposed model can be easily implemented into commercial RF circuit simulators. It provides a novel solution to include
more » ... he frequency-variant characteristics into a circuit simulation. The silicon-verified accuracy is proved to be up to 25 GHz with an average error less than 2%. Additionally, equivalent circuit model for longer wires can be obtained by cascading smaller subsections together. The scalability of the propose model is demonstrated. Index Terms-Empirical formulas, lumped equivalent circuit model, modeling, RF CMOS interconnects, scalable, scattering parameters measurement, skin effect, substrate losses. Jian-Guo Ma (M'96-SM'97) received the B.Sc. and M.Sc. degrees (with hons.
doi:10.1109/tvlsi.2005.857177 fatcat:df3lddi7ujgjpge5okufssdiva