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Equivalent circuit model of on-wafer CMOS interconnects for RFICs
2005
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
This paper investigates the properties of the on-wafer interconnects built in a 0.18-m CMOS technology for RF applications. A scalable equivalent circuit model is developed. The model parameters are extracted directly from the on-wafer measurements and formulated into empirical expressions. The expressions are in functions of the length and the width of the interconnects. The proposed model can be easily implemented into commercial RF circuit simulators. It provides a novel solution to include
doi:10.1109/tvlsi.2005.857177
fatcat:df3lddi7ujgjpge5okufssdiva